1. Field of the Invention
The present invention relates to a static random access memory device, and more particularly to a static random access memory device with a power down function to reduce the consume current during a write cycle.
2. Description of the Related Art
Generally, in a static random access memory device (SRAM), a DC current flow between the terminals of a power source of the device continues during a write cycle. It is for this reason that the consume power of the SRAM is great. How the DC current flows inside the SRAM will be described with reference to FIG. 1.
A circuit configuration of only one column unit of an ordinary SRAM, viz., a configuration concerning a pair of bit lines BL1 and BL1, is illustrated in FIG. 1. As shown, a memory cell MC1 is made up of a flip-flop including a couple of resistors R1 and R2 and a couple of N channel MOSFETs Q11 and Q12, and a couple of N channel MOSFETs Q13 and Q14 for data transfer. When data "0" is loaded into this memory cell MC1, viz., the potential at node A is placed at "L" level and the potential at node B is placed at "H" level, data Din in "L" level is produced from a buffer 101, and data Din in "H" level, from a buffer 102. Under this condition, a word line WL1 and a column select line CSL1 are energized by a row decoder and a column decoder (both decoders are not shown), respectively. In turn, N channel MOSFETs Q1, Q2, Q13 and Q14 are turned on. Consequently, the node A is placed in "L" level by the data Din, while the node B, in "H" level by the data Din. In this way, data "0" is written into the memory cell MC1.
In the SRAM thus configured, the potential of "L" level at the node A turns off FET Q12, and the potential of "H" level at the node B turn on FET Q11. Accordingly, a current I1 indicated by a broken line flows from a power source terminal VDD to a ground VSS terminal, through N channel MOSFETs Q9, Q13 and Q11. Another current I2 also flows from a power source terminal VDD to a ground VSS terminal, through N channel MOSFETs Q9 and Q1, and the MOSFET Q8 in the buffer 101. During a write cycle, the word line WL1 and the column select line CSL1 are kept in an active state, so that during this period, the flow of the currents I1 and I2 continues. This leads to great consume current during the write cycle of the conventional SRAM.